1. Technical Field
This subject matter disclosed herein is generally directed to the field of packaging of integrated circuit devices, and, more particularly, to a packed IC device comprising an embedded flex circuit and various methods of making same.
2. Description of the Related Art
Integrated circuit technology uses electrical devices, e.g., transistors, resistors, capacitors, etc., to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever-increasing number of linked electrical devices so that the circuit may perform its intended function. As the number of transistors increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and/or on different wafers or chips. In general, it is desirable in the semiconductor industry to construct transistors which occupy less surface area on the silicon chip/die.
In the manufacture of semiconductor device assemblies, a single semiconductor die is most commonly incorporated into each sealed package. Many different package styles are used, including dual inline packages (DIP), zig-zag inline packages (ZIP), small outline J-bends (SOJ), thin small outline packages (TSOP), plastic leaded chip carriers (PLCC), small outline integrated circuits (SOIC), plastic quad flat packs (PQFP) and interdigitated leadframe (IDF). Some semiconductor device assemblies are connected to a substrate, such as a circuit board, prior to encapsulation. Manufacturers are under constant pressure to reduce the size of the packaged integrated circuit device and to increase the packaging density in packaging integrated circuit devices.
The assembly of a semiconductor device and a leadframe and die ordinarily includes bonding of the die to a paddle of the leadframe, and wire bonding the bond pads on the die to the inner leads, i.e., lead fingers, of the leadframe. The inner leads, semiconductor die and bond wires are then encapsulated, and extraneous parts of the leadframe excised. In one illustrative example, the leadframe strip comprises a thin metal foil that is configured for the mounting of one or more semiconductor die, e.g., one on each die mount paddle. The leadframe strip also includes parallel spaced side rails formed with a pattern of registry holes to facilitate handling by automatic machinery. In addition, the leadframe strip includes an arrangement of inner leads configured for attachment to the bond pads of the semiconductor die during a wire bonding step. The outer leads of the leadframe strip function as the external leads of the completed semiconductor device package for connection to an external device or structure, e.g., a circuit board. The leads are connected to the side rails by dam bars, and supported thereby. The die mount paddles are typically connected to each of the side rails by a paddle support bar, extending transversely with respect to the centerline of the leadframe strip.
Such traditional packaging techniques and arrangements may not be able to meet the demands for more densely packaged integrated circuit devices desired by semiconductor manufacturers and their customers.
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.